The invention relates generally to the testing of integrated circuits (ICs) and more particularly to a system and method for testing ICs by transient signal analysis.
Continuing increases in the complexity and density of integrated circuit (IC) components within a circuit chip have imposed an escalating challenge to the testing of circuitry. By one estimation, the cost of testing can contribute up to 20 percent of the total cost of manufacturing. To achieve economy of scales, it is critical that the cost of testing be minimized.
Minimizing cost in high-volume manufacturing requires that the testability of the IC be considered up front, since both time and money are required to achieve a desired level of quality. Various techniques for testing have existed for many years. In an IC production environment, quiescent power supply current (IDDQ) testing has been used to detect defects in the ICs. However, the effectiveness of IDDQ testing in deep-submicron technologies (e.g., 0.13 xcexcm processes) may be reduced due to high background currents, including sub-threshold leakage currents, and process drift variations.
The use of transient current or voltage testing techniques for the detection of defects addresses many problems associated with IDDQ testing. For one, transient current or voltage testing techniques are much less susceptible to variations induced by sub-threshold leakage currents. One such transient voltage testing technique is transient signal analysis (TSA). In a current TSA testing technique, an oscilloscope and digital signal processing (DSP) may be required. A concern associated with the use of an oscilloscope and DSP is that they add to the complexity, time and cost of manufacturing. Moreover, many transient current or voltage testing techniques do not account for process drift variations among the ICs. This is problematic, since a defect-free device-under-test (DUT) may be falsely rejected if it includes variations, such as transistor mobilities and threshold variations, that deviate from a defect-free reference IC, but which are within acceptable standards.
What is needed is a system and method for testing an IC by transient signal analysis, such that the complexity, time and cost of manufacturing, as well as false rejects due to process drift variations, are reduced.
A system and method for testing an integrated circuit (IC) by transient signal analysis includes a comparison circuit that is configured to generate a comparison signal from an IC transient signal and a reference signal. Typically, the comparison signal represents a difference between the IC transient signal and reference signal. The IC transient signal is specific to a monitored supply voltage to the IC. Circuitry operationally coupled to the comparison circuit manipulates the comparison signal to generate an output waveform for determining if the IC complies with a predetermined standard.
In a first embodiment, the system has a seven operational-amplifier (op-amp) configuration. At a first stage, a comparison circuit using two op-amps subtracts the IC transient signal from the reference signal to generate the comparison signal. At a second stage, an inverting amplifier inverts the comparison signal to generate an inverted signal. Optionally, the comparison signal is amplified by the inverting amplifier to generate an inverted amplified signal. The amplification provides an auxiliary gain to facilitate distinguishing variations within the signal. At a subsequent stage, a first rectifier in communication with the inverting amplifier receives the inverted amplified signal to output only first portions of the inverted amplified signal. The first portions may be the positive portions of the inverted amplified signal. The first rectifier is a single op-amp.
The inverted amplified signal generated by the inverting amplifier at the second stage is also received by a unity-gain inverter. The unity-gain inverter merely inverts the signal to generate a twice-inverted amplified signal. At the subsequent stage, a second rectifier receives the twice-inverted amplified signal to output only second portions of the twice-inverted amplified signal. Again, the second portions may be positive portions. The second rectifier is one op-amp and is in parallel with the first rectifier.
An adder-integrator circuit in communication with the first and second rectifiers adds the first portions of the inverted amplified signal and the second portions of the twice-inverted amplified signals and also identifies an output waveform area indicative of the first and second portions. The output waveform area is an absolute area of positive and negative portions within the output waveform. The adder-integrator is one op-amp.
In a second embodiment, the system has a ten op-amp configuration. At a first stage, a comparison circuit subtracts the IC transient signal from the reference signal to generate the comparison signal. The comparison signal is optionally amplified at a second stage to provide an auxiliary gain to further distinguish variations within the signal. If the optional amplification is not used, the second embodiment only includes nine op-amps. At a subsequent stage, a first rectifier in communication with the amplifier outputs first portions of the comparison signal. In one application, the first portions are positive portions of the comparison signal. The first rectifier includes two op-amps.
The comparison signal generated by the amplifier at the second stage is also received by a unity-gain inverter to invert the comparison signal. Subsequently, a second rectifier in communication with the unity-gain inverter outputs the second portions of the comparison signal. In one application, the second portions are positive portions of the comparison signal. The second rectifier includes two op-amps and is in parallel with the first rectifier.
A unity-gain adder receives and adds the first and second portions of the comparison signal. The unity-gain adder is one op-amp. An integrator in communication with the unity-gain adder identifies an output waveform area of the first and second portions. The output waveform area is an absolute area of positive and negative portions within the output waveform. The integrator is one op-amp.
As a further processing sequence, a second output waveform area is determined using the seven op-amp configuration or the ten op-amp configuration. The second output waveform area includes an absolute area of positive and negative portions within a second output waveform of a second comparison signal. The second comparison signal includes a difference between a second IC transient signal and a reference signal.
In one embodiment, the pass/fail status of the IC is established by applying statistical analysis. Accordingly, a correlator is provided to define a plot that is based on a first value corresponding to the output waveform area over a predefined time interval and a second value corresponding to the second output waveform area over an equivalent time interval. The X-Y coordinate that is defined by this pair is used to determine if the IC falls within a confidence level of a pass/fail standard.
An advantage of the invention is that the number of circuits needed for determining the pass/fail status of the IC is small, even in the ten op-amp configuration. This is potentially important, since it simplifies the hardware requirements needed for testing. Moreover, by using a small number of op-amps for determining the pass/fail status of the IC, the cost overhead in IC testing is reduced. Additionally, the use of statistical analysis to determine the pass/fail status of the IC is less susceptible to testing errors which might otherwise occur as a result of process drift variations among the ICs.